1. Field of the Invention
The present invention relates to bipolar transistors, and is particularly concerned with bipolar transistors in fast integrated circuits.
2. Description of the Prior Art
Silicon bipolar transistors are required for fast integrated circuits, as needed in data technology, consumer electronics and communications technology.
Further developments of bipolar transistors have been toward higher speeds, given higher packing density. In order to achieve higher integration, the demand of reducing the space requirement is made of the individual transistor.
What is referred to as the polysilicon self-aligned (PSA) transistor is now universally standard, this being described, for example, by W.M. Werner, et al in the "Modern Bipolar Technology for Gate Array and Memory Applications", Siemens Forschungs-und Entwicklungsbericht, Vol. 17, No. 5, 1988, pp. 221-226 For manufacturing the PSA transistor, a polycrystalline layer is applied onto a silicon substrate. The polycrystalline layer is doped with a material of a first conductivity type. A first oxide layer is deposited thereon. A window structure is produced in this double layer by etching down to the substrate surface, the active base being formed by implantation through the window structure. The sidewalls of the window are covered with oxide spacers. A second polycrystalline layer that is of a material of the opposite conductivity type with reference to the first polysilicon layer is then deposited onto the oxide layer, onto the sidewall spacers and onto the exposed surface of the substrate. The emitter is formed self-aligned relative to the active base by out-diffusion from the second polycrystalline layer into the substrate. The definition of the dimensions of the window and, therefore, of the dimensions of the emitter width that derives occurs by photolithography in the PSA transistor. Given small emitter widths, a deviation from reference dimensions is extremely probable. In a one-micrometer lithography, the effective emitter contact width amounts to about 0.6 .mu.m since the sidewall spacers have a finite extent. Given a tolerance in the lithography of at least .+-. 0.1 .mu.m per edge, one must therefore count on a tolerance of about 30% of the effective emitter width. The tolerance therefore becomes intolerable for smaller emitter widths.
Fluctuations in the size of the emitter area have an influence on the current density in the transistor. This enters in the optimization of the circuits with respect to currents, voltage drops, speed and dissipated power. Fluctuations on the order of magnitude of 30% are not acceptable for many circuits.
Pairs of transistors in which the transistors have identical doping profiles are often employed in differential amplifiers. For such pairs of transistors, the offset voltage, i.e. the control voltage with which the inputs of a differential amplifier must be occupied so that the output currents become of identical size, is dependent only on the differences of the effective emitter areas. For offset values of approximately 1mV. the emitter areas may differ by a maximum of about 4%.
The European Patent Application 0 239 825 Al discloses a bipolar transistor wherein the effective emitter widths are defined in self-aligned fashion, i.e. not via photolithography. A conductive layer is deposited onto the surface of a substrate that has a step-shaped elevation. The deposition occurs such that the edge of the step-shaped elevation is well covered. The layer is doped. An etching residue is produced at the vertical sidewall of the step-shaped elevation by anisotropic re-etching of the layer. The emitter is formed by out-diffusion from the etching residue into the substrate. The etching residue forms a part of the emitter terminal region. The effective emitter area in this transistor is defined by the common area of the substrate and of the etching residue. The extent of this effective emitter area is therefore dependent on the thickness of the conductive layer that is deposited and on the parameters used in the etching process. The tolerance of the effective emitter area is reduced to about 10% in this transistor.